2009-12-28

[Tccc] Multicore and Multithreaded Architectures and Algorithms (M2A2-2010) with ICA3PP 2010

Call for Papers

The 2010 International Workshop on Multicore and Multithreaded Architectures and Algorithms (M2A2 2010)
May 21-23, 2010, Busan, Korea

http://cse.stfx.ca/~ica3pp2010/CFP-M2A2-10.pdf

In conjunction with:

The 10th International Conference on Algorithms and Architectures for Parallel Processing (ICA3PP 2010)
http://cse.stfx.ca/~ica3pp2010/


Multicore systems are already dominating the processor market, and it is
expected that the number of cores will continue increasing in most of
the commercial systems, ranging from embedded to high-performance
systems. This trend is driven by the need to increase the efficiency of
the major system components: the cores, the memory hierarchy, and the
interconnection network.

To take advantage of the increasing number of cores efficient load
balancing and scheduling policies or strategies are required. In
addition, it remains a challenge to identify and productively program
applications for these systems with a resulting substantial performance
improvement.

On the other hand, the system designer must trade off performance versus
power consumption, which is a major concern in current microprocessors.
Therefore current design must focus on new architectures or
architectural mechanisms addressing this trade off.

Finally, most real-time embedded applications are requiring
high-performance computing and multicore and multithreaded processors
are becoming the typical design choice.

The aim of this workshop is to provide a forum for engineers and
scientists to address the resulting challenge and to present new ideas,
applications, and experience on all aspects of multicore and
multithreaded systems.

Authors are invited to submit high quality papers representing their
original work in (but not limited to) the following topics targeting
muticore multithreaded processors:
• Multicore and multithreaded architectures.
• Scheduling and load balancing.
• Multicore programming
• Parallel algorithms
• Power-aware architectures and computing.
• Embedded multicore real-time systems

Paper Submission and Publication:
Submit original unpublished papers in PDF formats at the workshop
submission system: http://www.editorialsystem.net/M2A2-2010. All
submitted manuscripts will be reviewed at least by three expert
reviewers. Submissions will be judged on originality, technical
strength, quality of presentation, and relevance to the workshop scope.
All accepted papers will be included in the ICA3PP-10 workshop
proceeding published by IEEE (Our proceedings will be included in EI and
other index). Final author manuscripts will be 8.5" x 11" (two columns
IEEE format), not exceeding 8 pages; max 2 extra pages are allowed at
additional cost. Helpful information for paper formatting can be found
in the website. Moreover, after author's notification, the Online Author
Kit will be given on this website. Please format your camera-ready
version according to this kit finally. Authors of accepted papers, or at
least one of them, are requested to register and present their work at
the conference, otherwise their papers will not be published.
Distinguished papers accepted and presented in M2A2 2010, after further
revisions, could be considered for publication in special issues of SCI
international journals.

Important Dates:
Paper Submission Deadline: February 2, 2010
Acceptance Notification: February 22, 2010
Camera Ready Due: February 28, 2010
Conference Dates: May 21, 2010

General Co-Chairs:
Houcine Hassan, Universidad Politecnica de Valencia, Spain
Julio Sahuquillo, Universidad Politecnica de Valencia, Spain

Steering Committee:
Laurence T. Yang, St Francis Xavier University, Canada
Jong Hyuk Park, Seoul National University of Technology, Korea

Program Committee :
Hideharu Amano, Keio University, Japan
Luca Benini, University of Bolonia, Italy
Zonghua Gu, University of Science and Technology, Hong Kong
Rajiv Gupta, University of California, Riverside, USA
Luis Gomes, Universidade Nova de Lisboa, Portugal
Houcine Hassan, Universidad Politecnica de Valencia, Spain
Seongsoo Hong, Seoul National University, Korea
Shih-Hao Hung, National Taiwan University, Taiwan
Eugene John, University of Texas at San Antonio, USA
Seon Wook Kim, Korea University, Korea
Jihong Kim, Seoul National University, Korea
Chang-Gun Lee, Seoul National University, Korea
Yoshimasa Nakamura, Kyoto University, Japan
Hiroshi Nakashima, Kyoto University, Japan
Sabri Pllana, University of Vienna, Austria
Julio Sahuquillo, Universidad Politecnica de Valencia, Spain
Zili Shao, The Hong Kong Polytechnic University, Hong Kong
Kenjiro Taura, University of Tokyo, Japan


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Contact information:
Houcine Hassan (husein@disca.upv.es)
Julio Sahuquillo (jsahuqui@disca.upv.es)
Department of Computer Engineering.
Universidad Politecnica de Valencia.
Camino de Vera, 14
46022 Valencia, Spain

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